Circuit and method for arbitrarily shifting M-sequence

ABSTRACT

A circuit, which shifts an M-sequence code with an arbitrary number of bits, is realized by a small circuit scale. D-type flip-flops  1-6  form a shift register for generating an M-sequence and having outputs d 0 -d 5  of respective stages, to which 2 5  bit shift inserting circuit  10  is connected in the manner of receiving the outputs d 0 -d 5  as respective inputs and of outputting outputs O 0 -O 5 , to which 2 4  bit shift inserting circuit  11  is connected in the manner of receiving the outputs O 0 -O 5  as respective inputs. In the same manner, a 2 3  bit shift inserting circuit  12 , a 2 2  bit shift inserting circuit  13 , a 2 1  bit shift inserting circuit  14 , and a 2 0  bit shift inserting circuit  15  are sequentially connected with one another. Each of bit shift inserting circuits  10-15  respectively shifts a predetermined bit when control signals b 5 -b 0  are “1”, and does not shift a bit when “0” so as to output an input as it is. Therefore, it is possible to obtain an arbitrary bit shift.

BACKGROUND OF THE INVENTION

The present invention relates to a circuit for generating an M-sequencecode (Maximum Length Code) which is used as a spread code such in afrequency spread communication (Spread Spectrum Communication), andparticularly to the circuit for shifting the M-sequence code with anarbitrary bit. An M-sequence is a kind of PN (Pseudorandom Noise), whichcan be easily generated by a shift register comprising D-type flip-flops1-6 having a feedback circuit using an exclusive OR circuit 7 as shownin FIG. 9, for example. Accordingly, the M-sequence code is often usedas a spread code in a spread spectrum communication.

In the spread spectrum communication, it is necessary for a receptionside to generate an inverse spread code which synchronizes and coincideswith the spread code, so that it is necessary to have a synchronizationby arbitrarily shifting the M-sequence which is used in spreading.

There has been known a conventional circuit disclosed in JP-A-8-181679(1996), which is one of conventional methods for arbitrarily shiftingthe M-sequence. The conventional technology is shown in FIG. 10.

In FIG. 10, entire data of the M-sequence or PN-sequence are stored in aROM look-up table 54. An address added to the ROM 54 includes a value ofwhich an N-bit binary counter 53 counts a system clock signal 56, and avalue of which an adder 52 adds an offset signal 55 which is held in aregister 51 based on an external designation. Since the addressincreases one by one at every one count of the clock signal 56 by thecounter 53, the ROM 54 outputs in the order a PN-sequence 57 storedtherein.

Further, the offset signal 55 is written in the register 51 to increasethe address with its amount so as to output a shift output signal as thePN-sequence 57, thereby enabling to arbitrarily shift the PN-sequence.

By the way, in the conventional example described above, it is necessaryto store entire of the M-sequence or PN-sequence in the ROM, and it isno problem if a stage number of the M-sequence is small.

However, in the case of the M-sequence having 42 stages such in FIG. 11,for example, a cycle is 2⁴²−1 bit which corresponds to about 4000 Gbit.There has not been a ROM for holding such large data, which isimpractical idea at the present time.

Further, FIG. 11 is a circuit diagram showing a circuit for generating along code as a kind of a spread code, which is used in the IS95 systemof CDMA (Code Division Multiple Access) in U.S.A. The circuit uses anM-sequence of a forty-second stage, and comprises registers 601-642,adders 643-648, AND gate circuits 649-690, a modulo adder 691, therebyobtaining a long code 693 of which a bit is random shifted correspondingto a value of a mask code 692 which is inputted in the AND gate circuits649-690.

The mask code 692 is used as a cipher key, and it is necessary that maskcodes are the same as each other in the transmission side and thereception side.

Accordingly, there has been no original purpose to shift the M-sequencewith an arbitrary number of bits by using the mask code. Therefore, itis necessary that a mask code corresponding to a shift amount thereof ispreviously obtained and stored for shifting the M-sequence. Accordingly,it is difficult to instantaneously shift it with an arbitrary number ofbits.

SUMMARY OF THE INVENTION

The objective of the present invention is to solve the above-mentionedtasks.

Moreover, the objective of the invention is to provide a technology forarbitrarily shifting an M-sequence, the circuit capable of generatingthe M-sequence, which is shifted with an arbitrary number of bits by asmall circuit scale.

The objective of the present invention is achieved by a circuit forarbitrarily shifting an M-sequence, which comprises shift registers ofN-stage and for generating an M-sequence, a plurality of two to theseveral power bits shift inserting circuits connected in series betweenan output N-bit of each stage of the shift register and the final outputN-bit.

Furthermore, each of the two to the several power bit shift insertingcircuits, comprises a two to several power bit shifting circuit forshifting an N-bit input signal with two to several power bits, and adata selector for outputting after changing over the N-bit input signaland an N-bit signal outputted from the two to several power bit shiftingcircuit corresponding to an external control signal, so as to output anN-bit output signal.

Moreover, the two to several power bit shift inserting circuit has anexponent of the power of two, which is an integral number of N from 0 toN−1.

Still furthermore, a circuit for arbitrarily shifting an M-sequencenecessarily has only a two to several power bit shift inserting circuitwhich has a specific integral number from 0 to N−1 as an exponent of thepower of two.

BRIEF DESCRIPTION OF THE DRAWINGS

This and other objects, features and advantages of the present inventionwill become more apparent upon a reading of the following detaileddescription and drawings, in which:

FIG. 1 is a block diagram showing a circuit for arbitrarily shifting anM-sequence according to an embodiment of the present invention;

FIG. 2 is a block diagram showing the 2⁵ bit shift inserting circuit 10,the 2⁴ bit shift inserting circuit 11, the 2³ bit shift insertingcircuit 12, the 2² bit shift inserting circuit 13, the 2¹ bit shiftinserting circuit 14, and the 2⁰ bit shift inserting circuit 15;

FIG. 3 is a block diagram showing the 2⁰ bit shift circuit;

FIG. 4 is a block diagram showing the 2¹ bit shift inserting circuit;

FIG. 5 is a block diagram showing the 2² bit shift circuit;

FIG. 6 is a block diagram showing the 2³ bit shift inserting circuit;

FIG. 7 is a block diagram showing the 2⁴ bit shift circuit;

FIG. 8 is a block diagram showing the 2⁵ bit shift inserting circuit;

FIG. 9 is a block diagram showing an example of six stage PN generatingcircuit;

FIG. 10 is a block diagram showing the first conventional example; and

FIG. 11 is a block diagram showing the second conventional example.

DESCRIPTION OF THE EMBODIMENTS

There will be described an embodiment according to the presentinvention.

There will be described first a principle of a bit shift of anM-sequence by using FIG. 1. Even though the register shown in FIG. 1 hassix stages, the principles are the same as that having stages more thansix.

It is assumed that each stage of in the register (which is constructedfrom D-type flip-flops 1-6) shown in FIG. 1, has values d0-d5 as shownin the figure. Values after one bit can be obtained by the presentvalues d0-d5 according to the following equation (1). $\begin{matrix}{\begin{pmatrix}d_{0} \\d_{1} \\d_{2} \\d_{3} \\d_{4} \\d_{5}\end{pmatrix}_{n + 1} = {\begin{pmatrix}0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 1 \\1 & 0 & 0 & 1 & 0 & 0\end{pmatrix}\quad \begin{pmatrix}d_{0} \\d_{1} \\d_{2} \\d_{3} \\d_{4} \\d_{5}\end{pmatrix}_{n}}} & (1)\end{matrix}$

where a product of the matrix operation is a logical product, a sum ofthe matrix operation is a logical sum, a suffix of “n” of a vectordenotes a presence, and a suffix of “n+k” of a vector denotes acondition after shifted by k bits.

When the above-described matrix and vector are simplified, they can berepresented by the equation as follows: $\begin{matrix}{{A = \begin{pmatrix}0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 1 \\1 & 0 & 0 & 1 & 0 & 0\end{pmatrix}},{{\overset{\_}{d}}_{n} = \begin{pmatrix}d_{0} \\d_{1} \\d_{2} \\d_{3} \\d_{4} \\d_{5}\end{pmatrix}}} & (2)\end{matrix}$

If the condition can be represented as above-described equation, valuesafter shifted with k bits can be represented by the following equation:

{overscore (d)} _(n+k) =A ^(k) ·{overscore (d)} _(n)  (3)

A “k” can be represented by a power of two as follows: $\begin{matrix}{k = {\sum\limits_{i = 0}^{5}\quad {{b_{i} \cdot 2^{i}}\quad \left( {b_{i} = {0\quad {or}\quad k}} \right)}}} & (4)\end{matrix}$

Accordingly, the following equation can be obtained as a conclusion:$\begin{matrix}{\overset{\_}{d_{n + k}} = {\prod\limits_{i = 0}^{5}\quad {{A^{b_{i} \cdot 2^{i}} \cdot {\overset{\_}{d}}_{n}}\quad \left( {b_{i} = {0\quad {or}\quad k}} \right)}}} & (5)\end{matrix}$

Accordingly, on the basis of a matrix A which is shifted with k bits, amatrix of two to several power of the matrix A is previously obtained,and the obtained matrix is caused to be respectively operated with theoriginal vector corresponding to a binary number representation bi of avalue of k, thereby introducing the values of the register after shiftedwith k bit.

According to the above-described contents, the present invention canobtain an output shifted by k bits, in the manner of obtaining a productof two to several power of the matrix A, and of providing a shiftcircuit corresponding to an operation of the product, the shift circuitwhich operates the above operation when the binary number representationbi of k is “1”, and operates by bypassing the above operation to d0-d5when the representation bi is “0”. This is the basis of the presentinvention.

The followings are showing the calculation of two to several powerproducts of the matrix A in the M-sequence having six stages.

In the case of a large number of stages, the calculation method is thesame as that of the six stages. $\begin{matrix}\begin{matrix}{{A^{2^{0}} = {A = \begin{pmatrix}0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 1 \\1 & 0 & 0 & 1 & 0 & 0\end{pmatrix}}},} \\{{A^{2^{1}} = {{A^{2^{0}} \cdot A^{2^{0}}} = {A^{2} = \begin{pmatrix}0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 1 \\1 & 0 & 0 & 1 & 0 & 0 \\0 & 1 & 0 & 0 & 1 & 0\end{pmatrix}}}},} \\{{A^{2^{2}} = {{A^{2^{1}} \cdot A^{2^{1}}} = {A^{4} = \begin{pmatrix}0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 1 \\1 & 0 & 0 & 1 & 0 & 0 \\0 & 1 & 0 & 0 & 1 & 0 \\0 & 0 & 1 & 0 & 0 & 1 \\1 & 0 & 0 & 0 & 0 & 0\end{pmatrix}}}},} \\{{A^{2^{3}} = {{A^{2^{2}} \cdot A^{2^{2}}} = {A^{8} = \begin{pmatrix}0 & 0 & 1 & 0 & 0 & 1 \\1 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0\end{pmatrix}}}},} \\{{A^{2^{4}} = {{A^{2^{3}} \cdot A^{2^{3}}} = {A^{16} = \begin{pmatrix}0 & 1 & 0 & 0 & 1 & 0 \\0 & 0 & 1 & 0 & 0 & 1 \\1 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0\end{pmatrix}}}},}\end{matrix} \\{A^{2^{5}} = {{A^{2^{4}} \cdot A^{2^{4}}} = {A^{32} = \begin{pmatrix}0 & 0 & 0 & 0 & 0 & 1 \\1 & 0 & 0 & 1 & 0 & 0 \\0 & 1 & 0 & 0 & 1 & 0 \\0 & 0 & 1 & 0 & 0 & 1 \\1 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0\end{pmatrix}}}}\end{matrix}$

That is, the matrix of A to 2⁰ (two to zero power) power is a matrixthat an M-sequence of six stages (six bits) is caused to be shifted withone bit. Further, the matrix of A to 2¹ (two to the first power) poweris a matrix that an M-sequence of six stages (six bits) is caused to beshifted with two bits. Further, the matrix of A to 2² (two to the secondpower) power is a matrix that an M-sequence of six stages (six bits) iscaused to be shifted with four bits. Further, the matrix of A to 2³ (twoto the third power) power is a matrix that an M-sequence of six stages(six bits) is caused to be shifted with eight bits. Further, the matrixof A to 2⁴ (two to the fourth power) power is a matrix that anM-sequence of six stages (six bits) is caused to be shifted with sixteenbits. Further, the matrix of A to 2⁵ (two to the fifth power) power is amatrix that an M-sequence of six stages (six bits) is caused to beshifted with thirty-two bits.

It is possible to arbitrarily shift an M-sequence by means of acombination of these matrices (or determinants). For example, it will besupposed that an M-sequence of six stages (six bits) is caused to beshifted with five bits.

In the case of shifting the M-sequence with five bits, it is sufficientthat one bit is shifted first, and then four bits are shifted.Accordingly, if the matrix of A to 2⁰ power and the matrix A to 2² powerare multiplied in the order to the M-sequence, it is possible to obtainan M-sequence in which five bits are shifted.

Next, there will be described in detail a shift circuit according to thepreferred embodiment of the present invention with reference to theattached drawings.

FIG. 1 is a block diagram showing a configuration of a circuit forarbitrarily shifting an M-sequence according to one embodiment of thepresent invention.

The circuit of this embodiment comprises a plurality of D-typeflip-flops 1-6 constituting a shift register for generating anM-sequence, an exclusive OR gate 7, a 2⁵ (two to the fifth power) bitshift inserting circuit 10 for inputting a plurality of outputs d₀, d₁,d₂, d₃, d₄ and d₅ which are outputted from the D-type flip-flops 6, 5,4, 3, 2, 1, respectively, a 2⁴ (two to the fourth power) bit shiftinserting circuit 11 for inputting an output of the 2⁵ bit shiftinserting circuit 10, a 2³ (two to the third power) bit shift insertingcircuit 12 for inputting an output of the 2⁴ bit shift inserting circuit11, a 2² (two to the second power) bit shift inserting circuit 13 forinputting an output of the 2³ bit shift inserting circuit 12, a 2¹ (twoto the first power) bit shift inserting circuit 14 for inputting anoutput of the 2² bit shift inserting circuit 13, and a 2⁰ (two to thezero power) bit shift inserting circuit 15 for inputting an output ofthe 2¹ bit shift inserting circuit 14. Respective bit shift insertingcircuits 10-15 perform a predetermined bit shift when control signalb₅-b₀ are “1”, and do not perform the bit shift when the signals are “0”to output an input as it is. By this, it is possible to obtain a shiftof the bit as follows: $\begin{matrix}{k = {\sum\limits_{i = 0}^{5}\quad {b_{i} \cdot 2^{i}}}} & (6)\end{matrix}$

Here, there will be described a control signal.

The control signal is outputted from a control circuit 100. When thecontrol circuit 100 receives an order for shifting with k bit(s), k isrewritten by a binary scale representation of six figures. For example,there is 000101 when k is five, and there is 100000 when k is 32,respectively. A number of the first figure is outputted by a controlsignal b₀, a number of the second figure is outputted by a controlsignal b₁, a number of the third figure is outputted by a control signalb₂, a number of the fourth figure is outputted by a control signal b₃, anumber of the fifth figure is outputted by a control signal b₄, and anumber of the sixth figure is outputted by a control signal b₅,respectively.

For example, when five bits are shifted, there is 000101 when five isrepresented by a binary scale. Accordingly, the control signal b₀ is“1”, the control signal b₁ is “0”, the control signal b₂ is “1”, thecontrol signal b₃ is “0”, the control signal b₄ is “0”, and the controlsignal b₅ is “0”, respectively.

The bit shift inserting circuits 10-15 have the above-describedoperation when each of control signals is inputted.

In this case, the control signal b₅=0 is inputted into a 2⁵ bit shiftinserting circuit 10, the control signal b₄=0 is inputted into a 2⁴ bitshift inserting circuit 11, the control signal b₃=0 is inputted into a2³ bit shift inserting circuit 12, the control signal b₂=1 is inputtedinto a 2² bit shift inserting circuit 13, the control signal b₁=0 isinputted into a 2¹ bit shift inserting circuit 14, and the controlsignal b₀=1 is inputted into a 2⁰ bit shift inserting circuit 15,respectively.

The 2⁵-bit shift inserting circuit 10 does not shift a bit by thecontrol signal, and outputs the input as it is. The 2⁴-bit shiftinserting circuit 11 does not shift a bit in the output of the 2⁵-bitshift inserting circuit 10 by the control signal, and outputs the inputas it is. The 2³-bit shift inserting circuit 12 does not shift a bit inthe output of 2⁴-bit shift inserting circuit 11 by the control signal,and outputs the input as it is. The 2²-bit shift inserting circuit 13outputs after shifting the output of the 2³-bit shift inserting circuit12 with four bits by the control signal. The 2¹-bit shift insertingcircuit 14 does not shift a bit in the output of the 2²-bit shiftinserting circuit 13 by the control signal, and outputs the input as itis. The 2⁰-bit shift inserting circuit 15 outputs after shifting theoutput of the 2¹-bit shift inserting circuit 11 with one bit by thecontrol signal.

Accordingly, a bit string outputted from the 2⁰-bit shift insertingcircuit 15 is that the M-sequence outputted from the shift register hasbeen shifted with five bits.

FIG. 2 is a block diagram showing each of the 2⁵-2⁰ bit shift insertingcircuits 10-15 shown in FIG. 1.

Each of the 2^(n) bit shift inserting circuits (n=5, 4, . . . , and 0,)10-15 comprises input terminals I₀, I₁, I₂, I₃, I₄, I₅, and CNT, a 2^(n)bit shift inserting circuit 21 for performing a predetermined bit shiftwith respect to a plurality of inputs A₀-A₅ of the input terminals I₀-I₅so as to output a plurality of outputs B₀-B₅, and a data selector 22 foroutputting the outputs B₀-B₅ when the input terminal CNT has a controlsignal being “1” and for alternatively outputting the inputs A₀-A₅ ofthe input terminals I₀-I₅ when the control signal b is “0”, respectivelyfrom output terminals O₀-O₅.

FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7 and FIG. 8 are block diagramrespectively showing the 2⁰ bit shift circuit, the 2¹ bit shift circuit,the 2² bit shift circuit, the 2³ bit shift circuit, the 2⁴ bit shiftcircuit, and the 2⁵ bit shift circuit.

The 2⁰ bit shift circuit has an exclusive OR circuit 31 for taking anexclusive OR of the input A₀ of the input terminal I₀ and the input A₃of the input terminal I₃. The 2⁰ bit sift circuit outputs the inputs A₁,A₂, A₃, A₄ and A₅ of the input terminals I₁, I₂, I₃, I₄ and I₅respectively to the output terminals O₁, O₂, O₃, O₄ and O₅, and outputsthe output of the exclusive OR circuit 31 to the output terminal O₅.

The 2¹ bit shift circuit has an exclusive OR circuit 32 for taking anexclusive OR of the input A₀ of the input terminal I₀ and the input A₃of the input terminal I₃, and an exclusive OR circuit 33 for taking anexclusive OR of the input A₁ of the input terminal I₁ and the input A₄of the input terminal I₄. The 2¹ bit sift circuit outputs the inputs A₂,A₃, A₄ and A₅ of the input terminals I₂, I₃, I₄ and I₅, respectively tothe output terminals O₀, O₁, O₂, and O₃, and outputs the outputs of theexclusive OR circuits 32 and 33 to the output terminals O₄ and O₅.

The 2² bit shift circuit has an exclusive OR circuit 34 for taking anexclusive OR of the input A₀ of the input terminal I₀ and the input A₃of the input terminal I₃, an exclusive OR circuit 35 for taking anexclusive OR of the input A₁ of the input terminal I₁ and the input A₄of the input terminal I₄, and an exclusive OR circuit 36 for taking anexclusive OR of the input A₂ of the input terminal I₂ and the input A₅of the input terminal I₅. The 2² bit sift circuit outputs the inputs A₄,A₅, and A₀ of the input terminals I₄, I₅ and I₀, respectively to theoutput terminals O₀, O₁ and O₅, and outputs the outputs of the exclusiveOR circuits 34, 35 and 36 to the output terminals O₂, O₃ and O₄.

The 2³ bit shift circuit has an exclusive OR circuit 37 for taking anexclusive OR of the input A₂ of the input terminal I₂ and the input A₅of the input terminal I₅. The 2³ bit sift circuit outputs an output ofthe exclusive OR circuit 37 and the inputs A₀, A₁, A₂, A₃ and A₄ of theinput terminals I₀, I₁, I₂, I₃ and I₄ respectively to the outputterminals O₁, O₁, O₂, O₃, O₄ and O₅.

The 2⁴ bit shift circuit has an exclusive OR circuit 38 for taking anexclusive OR of the input A₁ of the input terminal I₁ and the input A₄of the input terminal I₄, an exclusive OR circuit 39 for taking anexclusive OR of the input A₂ of the input terminal I₂ and the input A₅of the input terminal I₅. The 2⁴ bit sift circuit outputs each ofoutputs from the exclusive OR circuits 38 and 39 and the inputs A₀, A₁,A₂, and A₃ of the input terminals I₀, I₁, I₂ and I₃ respectively to theoutput terminals O₀, O₁, O₂, O₃, O₄ and O₅.

The 2⁵ bit shift circuit has an exclusive OR circuit 40 for taking anexclusive OR of the input A₀ of the input terminal I₀ and the input A₃of the input terminal I₃, an exclusive OR circuit 41 for taking anexclusive OR of the input A₁ of the input terminal I₁ and the input A₄of the input terminal I₄, and an exclusive OR circuit 42 for taking anexclusive OR of the input A₂ of the input terminal I₂ and the input A₅of the input terminal I₅. The 2⁵ bit sift circuit outputs the inputs A₅,each of outputs of the exclusive OR circuits 40, 41 and 42, the input A₀of the input terminal I₀, and the input A₁ of the input terminal I₁,respectively to the output terminals O₀, O₁, O₂, O₃, O₄ and O₅.

The above-described constitution can easily configured from each valueof the power in the matrix A as has been described above.

Even though the six-stage M-sequence has been described above, it isclear that the present invention can apply to another M-sequence havinga plurality number of stages more than six stages.

As has been described above, since the present invention can realize asmall circuit scale of the circuit that shifts the M-sequence with anarbitrary bit, it is possible to miniaturize the unit, to decrease anelectric power consumption, and to reduce a cost.

What is claimed is:
 1. A circuit for arbitrarily shifting an M-sequence,comprising: N stages of shift registers for generating the M-sequence;and a plurality of two to several power bit shift inserting circuitswhich are connected in series between N bit outputs of each stage ofsaid shift register and a final N bit output.
 2. The circuit forarbitrarily shifting the M-sequence, as set forth in claim 1, whereineach of said two to several power bit shift inserting circuits comprisestwo to several power bit shifting circuit for shifting an input signalof N-bit with two to several power bits so as to output an output signalof N-bit, and a data selector for changing over said input signal ofN-bit and said output signal of N-bit corresponding to a control signalsupplied from an outside, so as to output an output signal of N-bitthereof.
 3. The circuit for arbitrarily shifting the M-sequence, as setforth in claim 1, wherein each of said two to several power bit shiftinserting circuits has an N-number of integral from 0 to N−1.
 4. Thecircuit for arbitrarily shifting the M-sequence, as set forth in claim1, wherein each of said two to several power bit shift insertingcircuits having the N-number of integral exponents from 0 to N−1, hasnecessarily only one exponent.
 5. A circuit for arbitrarily shifting anM-sequence, comprising: a shift register having N stages and forgenerating an M-sequence of N-bit; control means for outputting as acontrol signal, in a case of shifting said M-sequence of N-bit with kbit or bits, a binary number which is converted from said k into abinary number representation; and an N number of two to several powerbit shift inserting circuits which are connected in series between N-bitoutputs of each stage of said shift registers and final N-bit outputs:wherein each of said two to several power bit shift inserting circuitshas one integral from 0 to N−1 as an exponent of power of two, andwherein each of said two to several power bit shift inserting circuitsinputs an input signal corresponding to each of figures in said controlsignal which is represented by said binary number, shifts said inputsignal of N-bit with a bit of an exponent power of two when said controlsignal is 1, and outputs said input signal of N-bit, as it is, when saidcontrol signal is
 0. 6. The circuit for arbitrarily shifting theM-sequence, as set forth in claim 5, wherein each of said two to severalpower bit shift inserting circuits comprises: a two to several power bitshifting circuit for shifting said input signal of N-bit with two toseveral power bits; and a data selector for changing over said inputsignal of N-bit and an output signal of n-bit which is outputted fromsaid two to several power bit shifting circuit corresponding to saidcontrol signal so as to output an output signal of n-bit.
 7. The circuitfor arbitrarily shifting the M-sequence, as set forth in claim 6,wherein each of said two to several power bit shift inserting circuitshas an exponent of power of two, which is a specific integral from 0 toN−1 for avoiding an interposition.
 8. A circuit for arbitrarily shiftingan M-sequence, comprising: N stages shift registers for generating theM-sequence; an N number of two to several power bit shifting circuitshaving an exponent of power of two which is any one of integrals from 0to N−1, for shifting an input of N-bit with bits of power of an exponentof two: wherein, in a case of shifting said M-sequence of N-bitoutputted from said shift register with k bits, a combination ofshifting with k bits is selected from said N number of two to severalpower bit shifting circuits, an N-bit which is outputted from said shiftregister is inputted to a selected two to several power bit shiftingcircuit, a bit string of which k bit/bits is/are shifted is outputted.9. The circuit for arbitrarily shifting the M-sequence, as set forth inclaim 8, wherein each of said two to several power bit shift insertingcircuits has an exponent of power of two, which is a specific integralfrom 0 to N−1 for avoiding an interposition.
 10. The circuit forarbitrarily shifting the M-sequence, as set forth in claim 8, whereineach of said two to several power bit shift inserting circuitscomprises: a two to several power bit shifting circuit for shifting saidinput signal of N-bit with two to several power bits; and a dataselector for changing over said input signal of N-bit and an outputsignal of n-bit which is outputted from said two to several power bitshifting circuit corresponding to said control signal so as to output anoutput signal of n-bit: wherein said two to several power bit siftinserting circuits are connected in series with one another between anoutput N-bit of each stage of said sift registers and a final outputN-bit, thereby outputting said final output N-bit which is shifted fromsaid output N-bit of each stage of said shift register.
 11. A method forshifting an M-sequence of N-bit with k bits, comprising: a step ofgenerating the M-sequence of N-bit; a step of selecting a combinationwhich causes said M-sequence of N-bit to be shifted with k bits by shiftmeans for shifting said M-sequence of N-bit with two to zero power bit,two to the first power bits, . . . , and two to the (N−1)-th power bit;and a step of obtaining an M-sequence which is shifted with k bits byinputting an M-sequence of N-bit into said selected shift means andsequentially shifting said M-sequence of N-bit.
 12. A method forshifting an M-sequence of N-bit with k bits, comprising: a step ofproviding a matrix A which causes said M-sequence of N-bit to be shiftedwith one bit; and a step of obtaining an M-sequence shifted with k bitsby multiplying said M-sequence of N-bit by said matrix A to the k-thpower.
 13. The method for shifting the M-sequence of N-bit with k bits,as set forth in claim 12, wherein two to zero power, two to the firstpower, . . . , and two to the (N-1)-th power are provided for saidmatrix A which shifts said M-sequence of N-bit with one bit; when saidM-sequence of N-bit is shifted with k bits, a combination of matrices atshifting with k bits is selected from matrices which are previouslyprovided; and the selected matrix is multiplied to said M-sequence ofN-bit, thereby shifting said M-sequence of N-bit with k bits.